The Atari 7800 combines the 2600 hardware with the MARIA custom graphics chip. In 7800 mode, the system provides 4K RAM, MARIA-driven video, TIA audio, and 6532 I/O at 1.79 MHz via the Sally (6502) processor.
6502 variant with HALT line for DMA. Runs at 1.79 MHz, slows to 1.19 MHz on TIA/RIOT access. Also used in the Atari 5200.
Custom graphics chip — heart of the 7800. Handles all video via Display List driven DMA. Supports 160 and 320 pixel modes with 8 color palettes.
Partially accessible in 7800 mode ($0000-$001F). Used for sound generation (2 channels) and fire button / paddle input reading.
I/O only in 7800 mode — no reliable RAM/timers. Reads joystick directions, console switches (pause, select, reset, difficulty).
Two 6116 2Kx8 chips occupy $1800–$27FF. Shadow mappings extend into zero page ($0040–$00FF) and stack page ($0140–$01FF) for fast access. Display Lists must reside in RAM.
Extended connector with all 16 address lines, R/W line for cart RAM, phase-2 clock for co-processors, audio/video mix-in lines, and HALT line to distinguish MARIA vs SALLY accesses.
MARIA uses a scanline-based approach similar to coin-op hardware. Each raster is composed by writing graphic fragments into Line RAM, specifying horizontal position, palette, and data address. Two Line RAM buffers alternate: one displays while the other is constructed via DMA.
No players/missiles/playfield concept. Instead, objects are placed by horizontal position into a bitmap-style Line RAM. Objects overlap with last-specified-on-top priority. Each pixel references one of 8 palettes with 3 colors + transparent.
Eight palettes, 3 colors each. Color zero of any palette = transparent. The BACKGRND register sets the background color.
4 bits color + 4 bits luminosity = 256 available hues. Palette registers: P0C1–P7C3 (write-only).
Mode selection combines Write Mode (set per-header via 5-byte DL entry) and Read Mode (set via CTRL register). Click a mode to explore:
| MODE | WRITE MODE (DL) | READ MODE (CTRL) | RESOLUTION | COLORS/PX |
|---|---|---|---|---|
| 160A | 0 | 00 | 160×H | 2 bits → 3+trans |
| 160B | 1 | 00 | 160×H | 4 bits → 12+trans |
| 320A | 0 | 11 | 320×H | 1 bit → 1+trans |
| 320B | 1 | 10 | 320×H | 2 bits → Pal 0|4 |
| 320C | 1 | 11 | 320×H | 1+palette bits |
| 320D | 0 | 10 | 320×H | Pal bits → color |
Standard 4-byte Display List entry for direct mode sprites/objects:
BYTE 1: Palette (bits 7-5) | Width in 2's complement (bits 4-0). If byte 1 = 0 → end of DL.
Extended 5-byte header enables indirect (character) mode and write-mode switching:
BYTE 1: Write Mode (bit 7), bit 6 must be 1, Indirect flag (bit 5), bits 4-0 = 0
The Display List List (DLL) is a series of 3-byte entries pointing to Display Lists and defining zones:
BYTE 0: DLI | Holey DMA flags | Offset (zone height − 1)
A zone is a group of rasters defined by one DLL entry. Zone height = OFFSET + 1 (up to 16 lines). Larger zones = less RAM for DLLs and Display Lists, but objects need zero-padding for smooth vertical scrolling.
For a 16-high zone, an 8px (2 byte) wide object at the bottom line needs 15 lines of zeros above it. Holey DMA solves this by interpreting certain addresses as zeros without needing actual zero data.
H16: Odd 4K blocks above $8000 treated as zeros (for 16-line zones).
H8: Odd 2K blocks above $8000 treated as zeros (for 8-line zones).
These "hole" areas can contain code, tables, or other graphics used in non-holey zones. Only 3 DMA cycles penalty per holey read.
Calculate DMA cycle usage for a scanline. Total available: 454 MARIA cycles per line (7.16 MHz). DMA begins 7 CPU cycles (28 MARIA cycles) into each scanline.
TIA provides 2 independent audio channels. Each has tone control (AUDC), frequency divider (AUDF), and volume (AUDV). Accessible at $0000–$001F. Any TIA access slows CPU to 1.19 MHz.
| ADDR | REG | BITS | FUNCTION |
|---|---|---|---|
| $15 | AUDC0 | 4 | Audio Control Ch.0 — tone/noise type |
| $16 | AUDC1 | 4 | Audio Control Ch.1 — tone/noise type |
| $17 | AUDF0 | 5 | Audio Frequency Ch.0 — divides 30KHz |
| $18 | AUDF1 | 5 | Audio Frequency Ch.1 — divides 30KHz |
| $19 | AUDV0 | 4 | Audio Volume Ch.0 — 0=off, 15=max |
| $1A | AUDV1 | 4 | Audio Volume Ch.1 — 0=off, 15=max |
| VALUE | SOUND TYPE |
|---|---|
| $0 | Silence (divided by 1) |
| $1 | 4-bit polynomial |
| $2 | ÷15 → 4-bit poly |
| $3 | 5-bit poly → 4-bit poly |
| $4/$5 | ÷2 pure tone |
| $6 | ÷31 pure tone |
| $7 | 5-bit poly ÷2 |
| $8 | 9-bit polynomial |
| $9 | 5-bit polynomial |
| $A | ÷31 pure tone |
| $B | Last 4 bits high |
| $C/$D | ÷6 pure tone |
| $E | ÷93 pure tone |
| $F | 5-bit poly ÷6 |
| ADDR | NAME | R/W | DESCRIPTION |
|---|---|---|---|
| $20 | BACKGRND | W | Background color |
| $21-$23 | P0C1-P0C3 | W | Palette 0 colors 1-3 |
| $24 | WSYNC | W | Wait for horizontal sync |
| $25-$27 | P1C1-P1C3 | W | Palette 1 colors 1-3 |
| $28 | MSTAT | R | Bit 7: VBLANK status (1=VBLANK on) |
| $29-$2B | P2C1-P2C3 | W | Palette 2 colors 1-3 |
| $2C | DPPH | W | Display List List pointer high |
| $2D-$2F | P3C1-P3C3 | W | Palette 3 colors 1-3 |
| $30 | DPPL | W | Display List List pointer low |
| $31-$33 | P4C1-P4C3 | W | Palette 4 colors 1-3 |
| $34 | CHARBASE | W | Character base high address (indirect mode) |
| $35-$37 | P5C1-P5C3 | W | Palette 5 colors 1-3 |
| $38 | OFFSET | W | Internal — set by DLL entries |
| $39-$3B | P6C1-P6C3 | W | Palette 6 colors 1-3 |
| $3C | CTRL | W | MARIA control register |
| $3D-$3F | P7C1-P7C3 | W | Palette 7 colors 1-3 |
| ADDR | NAME | R/W | DESCRIPTION |
|---|---|---|---|
| $01 | INPTCTRL | W | Mode control (7800/2600 switching) |
| $08 | INPT0 | R | Paddle 0 / P0 right button (2-btn mode) |
| $09 | INPT1 | R | Paddle 1 / P0 left button (2-btn mode) |
| $0A | INPT2 | R | Paddle 2 / P1 right button (2-btn mode) |
| $0B | INPT3 | R | Paddle 3 / P1 left button (2-btn mode) |
| $0C | INPT4 | R | P0 fire button (bit 7=0 pressed) |
| $0D | INPT5 | R | P1 fire button (bit 7=0 pressed) |
| $15 | AUDC0 | W | Audio control channel 0 |
| $16 | AUDC1 | W | Audio control channel 1 |
| $17 | AUDF0 | W | Audio frequency channel 0 |
| $18 | AUDF1 | W | Audio frequency channel 1 |
| $19 | AUDV0 | W | Audio volume channel 0 |
| $1A | AUDV1 | W | Audio volume channel 1 |
| ADDR | NAME | R/W | DESCRIPTION |
|---|---|---|---|
| $280 | SWCHA | R/W | Port A — joystick directions / controller I/O |
| $281 | CTLSWA | R/W | Port A DDR (0=input, 1=output) |
| $282 | SWCHB | R/W | Port B — console switches |
| $283 | CTLSWB | R/W | Port B DDR |
| $284 | INTIM | R | Interval timer read (unreliable w/DMA) |
| $294 | TIM1T | W | Set 1-clock interval (838 ns) |
| $295 | TIM8T | W | Set 8-clock interval (6.7 µs) |
| $296 | TIM64T | W | Set 64-clock interval (63.6 µs) |
| $297 | T1024T | W | Set 1024-clock interval (858.2 µs) |
Click any region to see details. Shadow regions provide fast zero-page and stack access to the 6116 RAM.
263 rasters per frame (~60 Hz)
Visible screen: rasters 16–258
Safe area: rasters 41–233 (192 scanlines)
Scanline: 227 pixels = 454 MARIA cycles = 113.5 CPU cycles
313 rasters per frame (~50 Hz)
Visible screen: rasters 16–308
Safe area: rasters 41–281 (240 scanlines)
Scanline: 227 pixels = 454 MARIA cycles = 113.5 CPU cycles
HBLANK: 67 pixels (134 MARIA cycles, 33.5 CPU cycles)
Visible: 160 pixels (320 MARIA cycles, 80 CPU cycles)
DMA starts 7 CPU cycles (28 MARIA cycles) into each scanline. MARIA @ 7.16 MHz, Sally @ 1.79 MHz (÷4 ratio).